1. Field of the Invention
The present invention relates, generally, to the controlled application of power to a circuit card during its insertion into a hot (powered) connector and, in one embodiment, to the two-step application of power to a Host Bus Adapter (HBA) card as it is connected to a powered Compact Peripheral Component Interconnect (CompactPCI) bus to minimize disturbances to the CompactPCI bus.
2. Description of Related Art
The Peripheral Component Interconnect (PCI) bus is a common and integral part of modern computer systems. However, PCI bus systems are not physically well-suited for environments that require zero downtime for reconfiguration or upgrades. The CompactPCI bus specification was developed to define a ruggedized version of the PCI bus for use in high reliability and availability systems. In a CompactPCI bus system, the bus is part of a powered backplane, and specialized circuit cards with staggered pins for the orderly application of power are coupled into the CompactPCI bus by insertion of the cards into slots on the backplane. One feature that the CompactPCI bus provides over a regular PCI bus is a Hot Swap feature, which is the ability to plug cards into and out of the backplane in a live (powered) environment without having to turn off system power. Hot Swap is a term and definition governed by the CompactPCI specification, PICMG 2.1, R2.0, Jan. 17, 2001, incorporated herein by reference.
The Hot Swap Compact PCI Specification defines a mechanical/electrical interface that enables HBAs to be installed in a hot (live) system without disturbing the operation of the system. The mechanical interface defines the HBA to the host backplane interface connector (CompactPCI connector). This CompactPCI connector provides three levels of pin staging which includes long, medium, and short pins. The long pins provide early power and ground, the medium pins provide additional power and ground and the signal interface, and the short pins provide the board select signals. There are two early power pins per supply voltage type. The electrical interface defines the maximum allowable input bulk capacitance (8.8 uF) seen by the early power pins and the maximum allowable inrush current per pin (1 A sustained, 2 A surge<100 us).
As illustrated in the exemplary diagram of FIG. 1, a CompactPCI bus 100 is typically part of a system which includes one or more processors or servers (CPU hosts) 102, main memory 104, Ethernet connections 106, bridges 108, adapter or interface cards 110, and the like. As with a regular PCI bus host, standard Windows NT and Linux software can run on a CompactPCI bus host. To implement Hot Swap capability, special circuitry is required in the hardware interface of the card, as well as system and card software drivers for cards that plug into the backplane. When a card is physically inserted or about to be extracted from a slot in the backplane, a latch on the card is closed or opened by an operator which triggers certain Hot Swap operations between the card and the host processor. These operations may load needed software drivers into host memory, or may delay the extraction of the card until all pending applications and transactions involving that card have been terminated.
There are a number of products currently being developed that implement a CompactPCI bus interface in adapter cards for peripheral buses and channels, such as a fibre channel network interface to be used in HBA designs for networking storage devices. Early CompactPCI bus interfaces coupled CompactPCI signals to an ASIC on the adapter card via FET switches (“quick switches”) and 50 kΩ pullup resistors tied to a precharge voltage of 1V. A Hot Swap controller chip provided the precharge voltage, and when backend power was applied, the FET switches were turned on to couple the ASIC to the CompactPCI bus.
In later designs, the functionality of the quick switches was incorporated into the ASIC, and core logic within the ASIC was used to control and put the ASIC I/O into a tristate mode. FIG. 2 illustrates a CompactPCI HBA 200 in which a CompactPCI bus 202 connects directly to an adapter ASIC 204 and a Hot Swap Controller 214 through a CompactPCI connector 206, the ASIC 204 being powered by 3.3V power 228 and a switching regulator 208 and further connected to backend logic 210 for interfacing to a fibre channel bus 212.
The Hot Swap Controller 214 of FIG. 2 is designed to gradually turn on backend power to the board by turning on field-effect transistor (FET) 216 while limiting the amount of inrush current being drawn at any one time. Early power provided by the 3.3VEP pins 228 provided via the CompactPCI connector 206 is intended to directly power up the logic that interfaces to the CompactPCI backplane, in particular the Hot Swap Controller 214 and the ASIC 204.
Note that in FIG. 2, the FET 216 has two source terminals, 218 and 220, which can be thought of as two separate FETs. The source terminal 218 provides power to the backend logic 210, while the source terminal 220 provides a feedback (FB) signal 224 to the Hot Swap Controller 214. The Hot Swap Controller 214 will compare its 3.3V power input 222 to the FB power input 224. When the two inputs are approximately equal, a “gate” signal 226 will be generated, which gradually turns on the FET 216 to provide power to backend logic 210.
The CompactPCI connector 206 is the interface to the CompactPCI backplane (not shown), which carries CompactPCI signals such as power, data, and control signals. The CompactPCI connector 206 contains several pins that supply power and ground to the CompactPCI card 200, including early power and ground pins which are longer than the others. In CompactPCI, for example, the backplane provides 3.3V early power and 5V early power. As the CompactPCI card 200 is being inserted into the CompactPCI connector 206, the early power and ground pins mate first, providing early power to the ASIC I/O and placing the I/O in a tristate (high impedance) mode to isolate the ASIC from the operating bus and eliminate the possibility of the ASIC erroneously driving the bus while it is powered up.
Each ASIC I/O contains a pullup resistor (e.g. 50 kΩ) connected to a precharge voltage (typically 1V). A Hot Swap controller 214 is also powered up by early power, and provides the precharge voltage to the ASIC I/O. The precharge voltage precharges the input or output capacitance for that pin. With a 50 kΩ impedance charged to 1V, each I/O has very little charge delivering capability and thus will have little effect on the bus when connected.
As the CompactPCI card 200 continues to be inserted, the shorter pins, which include additional power pins and the remainder of the signal pins, eventually mate. The time between the mating of the early power and ground pins and the remainder of the pins varies, but is typically on the order of 4 milliseconds (mS). Because the ASIC I/O has already been precharged and placed in a tristate mode by this time, the mating of the ASIC I/O to the CompactPCI backplane causes little disturbance to the signals on the backplane.
The CompactPCI specification places certain restrictions on devices connected to early power. According to the CompactPCI specification, early power is limited to 1 A of steady current and 2 A for a short period of time. In addition, the CompactPCI specification limits the amount of capacitance that can be connected to early power to a maximum of 8.8 microfarads (uF), so as not to burn pins or cause excessive disturbances on the system power when the early power pins are first mated to the CompactPCI card 200. This limitation on capacitance is necessary because if the early power had to suddenly charge up a large amount of capacitance, the inrush current might cause such a disturbance or dip in the system power that the system could inadvertently reset or otherwise not operate properly.
In previous CompactPCI adapter cards, CompactPCI interface logic was implemented in discrete logic or bridge integrated circuits (ICs) on the adapter card, and other logic for interfacing with other networks, such as a fibre channel ASIC, for example, was connected to the bridge. Because the interface logic was separated from other functions, it generally drew less power and could be connected directly to the early power pins along with a small capacitor without exceeding the previously described restrictions defined in the CompactPCI specification. Alternatively, because the interface logic drew less power, a linear regulator receiving an input voltage from the early power pins could have been employed to power the interface logic.
However, because ASIC densities have improved, it is now desirable to incorporate more digital circuitry within the ASIC. Thus, in the example of FIG. 2, the ASIC 204 on a modern fibre channel CompactPCI HBA may preferably include CompactPCI interface logic, a fibre channel controller and other logic. Because such multifunction ASICs are larger, they require more total power. Although the I/O of these larger ASICs do not require significantly more power, the ASIC core logic may require much higher power, possibly drawing current in excess of 4 A.
In the example of FIG. 2, a switching regulator 208 is employed to convert 3.3V power to 1.8V, for example, which is needed to power the ASIC core logic. Switching regulators repeatedly turn on and off to generate a DC voltage, and are preferred because they dissipate less power than linear regulators. Because so much power is required, linear regulators are not practical because they are not as efficient and dissipate more power than switching regulators. Note that the high current drive of the switching regulator 208 is not needed to place the ASIC I/O in a tristate configuration while the card 200 is in reset mode, but it is needed when the ASIC 204 is released from reset mode. Thus, the switching regulator 208 must be capable of supporting the ASIC 204 in its operational mode.
However, one drawback to switching regulators is that they require large input and output capacitances to smooth out perturbations on the input and output signals caused by the switching of the regulators. As illustrated in the example of FIG. 2, if a switching regulator capable of providing 4 A of current for the ASIC core logic is to be used, its input would have to be connected directly to the 3.3V early power with an input capacitor (see reference designator 230) much larger than the 8.8 uF allowed by CompactPCI. Thus, the power supply circuitry in the CompactPCI HBA 200 in the example of FIG. 2 is not a practical solution.
As can be seen from the above discussion, the desire to utilize ASICs with increased functionality creates a need for more power, which in turn requires the use of a switching regulator. However, the switching regulator requires high input and output capacitance, which violates the CompactPCI specification. Thus, a need exists for a CompactPCI power supply design that is able to utilize early power to power ASIC I/O during initialization and is also able to provide high current for the ASIC core logic during normal operation, while conforming to the CompactPCI specification.